1. Field of the invention
The present invention relates to a process for forming self-aligned metal-semiconductor ohmic contacts in integrated circuits and particularly on integrated MISFET structures.
2. Description of the prior art
The problem of electrically connecting the drain (and source) of MISFET structures (or more commonly of MOS transistors) to the respective metal tracks in integrated circuits becomes increasingly critical with the reduction of the sizes of these integrated structures. In FIG. 1 a conventional form of a contact between a metal layer 1 and the silicon 3 in an area comprised between two parallel gate lines, 4 and 5 respectively, commonly made of polycrystalline silicon and provided with lateral tapered spacers 6 of a dielectric material, commonly of silicon oxide, is depicted. The contact is formed through a "hole" which is purposely opened across the thickness of the dielectric layer 2 by means of a masking and etching process.
With decreasing dimensions, the lithographic difficulties relative to the definition of such micrometric windows through the masking resist and to the correct alignment of the mask and the processing difficulties relative to ensuring a good step coverage of the deposited metal within minuscule holes through the thickness of the dielectric layer 2 increase.
Lately several new techniques have been proposed for overcoming these technological problems and for making contacts of sub-micrometric size, necessary for fabricating VLSI and ULSI integrated devices, namely: improved techniques for tapering the holes for more easily achieving a good step coverage by the metal, improved lithographic techniques for enhancing the definition of areas with both dimensions smaller than one micrometer, often associated with special techniques for pre-filling the holes by means of metal plugs.
Generally a definite drawback of the known techniques is represented by the fact that the masking of the contacts remains a highly critical step requiring adequate levels of precision.